Global Unichip Corporation Uses Cadence Digital Implementation and Signoff Flow to Deliver Advanced-Node Designs for AI and HPC Applications

Cadence Innovus Implementation System and Voltus IC Power Integrity Solution enable GUC to achieve first-pass silicon success and meet GHz performance target for multi-billion gate designs

SAN JOSE, Calif.–(BUSINESS WIRE)–#EDA–Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Global Unichip Corporation (GUC) successfully deployed the Cadence® digital implementation and signoff flow and delivered advanced-node (N16, N12 and N7) designs for artificial intelligence (AI) and high-performance computing (HPC) applications. Through use of the Cadence Innovus Implementation System and the Voltus IC Power Integrity Solution, GUC achieved first-pass silicon success and met its GHz performance target for its multi-billion gate designs. For more information on the Cadence digital and signoff flow, please visit www.cadence.com/go/dsfcspr.

Traditional digital implementation and signoff tools lack the capacity GUC required for their multi-billion gate designs during the implementation and signoff stages. Alternative solutions on the market must be greatly scripted because they don’t offer a shared data model-level integration, requiring more manual work with increased design margins and limited performance. Where the traditional tools fall short, the tightly integrated Cadence solution helped GUC meet power, performance and area (PPA) targets and deliver their large-capacity, advanced designs on time.

The Innovus Implementation System improved the GUC design team’s productivity through its efficient hierarchical partitioning flow, advanced top-level floorplanning and block implementation and closure capabilities. The Voltus IC Power Integrity Solution enabled GUC to accurately analyze the top-level full-chip static/dynamic power, IR drop and electro-migration through its distributed processing capability using innovative extensive parallelism technology. The seamless shared data model-level integration between the Cadence tools provides GUC with an efficient way to close signoff EM-IR issues during block implementation, reducing costly iterations and engineering change orders (ECOs).

“As a leader in ASIC design, we need to deliver highly complex designs to customers quickly, particularly for emerging application areas like AI and HPC,” said Louis Lin, senior vice president of Design Services at GUC. “Through our deep collaboration with Cadence, we deployed their digital implementation and signoff tools quickly and easily, and the Cadence team also provided prompt support to further optimize our delivery cycle time and achieve our PPA targets.”

The Cadence Innovus Implementation System and Voltus IC Power Integrity Solution are part of the broader digital implementation and signoff full flow and provide customers with a faster path to design closure. The tools in the flow support the company’s Intelligent System Design strategy, enabling advanced-node system-on-chip (SoC) design excellence for AI and HPC applications.

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